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MC10EP445, MC100EP445 3.3V/5VECL 8-Bit Serial/Parallel Converter
Description
The MC10/100EP445 is an integrated 8-bit differential serial to parallel data converter with asynchronous data synchronization. The device has two modes of operation. CKSEL HIGH mode is designed to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode is designed to operate at twice the internal clock data rate of up to 5.0 Gb/s. The conversion sequence was chosen to convert the first serial bit to Q0, the second bit to Q1, etc. Two selectable differential serial inputs, which are selected by SINSEL, provide this device with loop-back testing capability. The MC10/100EP445 has a SYNC pin which, when held high for at least two consecutive clock cycles, will swallow one bit of data shifting the start of the conversion data from Dn to Dn+1. Each additional shift requires an additional pulse to be applied to the SYNC pin. Control pins are provided to reset and disable internal clock circuitry. Additionally, VBB pin is provided for single-ended input condition. The 100 Series contains temperature compensation.
Features
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MCxxx EP445 AWLYYWWG LQFP-32 FA SUFFIX CASE 873A
1
1
32
* * * * * * * * * * *
1530 ps Propagation Delay 5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode Differential Clock and Serial Inputs VBB Output for Single-Ended Input Applications Asynchronous Data Synchronization (SYNC) Asynchronous Master Reset (RESET) PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State CLK ENABLE Immune to Runt Pulse Generation Pb-Free Packages are Available*
QFN32 MN SUFFIX CASE 488AM
MCxx EP445 AWLYYWWG G
xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2010
September, 2010 - Rev. 13
1
Publication Order Number: MC10EP445/D
MC10EP445, MC100EP445
VCC SINA SINA VBB0 VEE SINB SINB SINSEL
32 RESET SYNC CKEN CLK CLK VBB1 CKSEL VCC 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 VCC PCLK PCLK Q0 VCC Q1 Q2 VCC
MC10EP445 MC100EP445
21 20 19 18 17
10
11
12
13
14
15
16
Q7
Q6
Q5 VCC VCC
Q4 Q3 VEE
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
Exposed Pad (EP) VCC SINA SINA VBB0 VEE SINB SINB SINSEL 32 RESET SYNC CKEN CLK CLK VBB1 CKSEL VCC 1 2 3 4 5 6 7 8 9 Q7 10 Q6 11 12 13 14 15 16 31 30 29 28 27 26 25 24 VCC 23 PCLK 22 PCLK
Table 1. PIN DESCRIPTION
Pin SINA*, SINA* SINB*, SINB* SINSEL* Q0-Q7 CLK*, CLK* PCLK, PCLK SYNC* CKSEL* CKEN* RESET* VBB0, VBB1 VCC VEE EP Function ECL Differential Serial Data Input A ECL Differential Serial Data Input B ECL Serial Input Selector Pin ECL Parallel Data Outputs ECL Differential Clock Inputs ECL Differential Parallel Clock Output ECL Conversion Synchronizing Input ECL Clock Input Selector Pin ECL Clock Enable Pin ECL Reset Pin Output Reference Voltage Positive Supply Negative Supply The exposed pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to VEE.
MC10EP445 MC100EP445
21 Q0 20 VCC 19 Q1 18 Q2 17 V CC
Q5 VCC VCC
Q4 Q3 VEE
Figure 2. 32-Lead QFN Pinout (Top View)
* Pins will default logic LOW or differential logic LOW when left open.
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MC10EP445, MC100EP445
Table 2. TRUTH TABLE
FUNCTION PIN SINSEL CKSEL Select SINB Input Q: PCLK = 8:1 CLK: Q = 1:1 CLK Q CKEN RESET SYNC Synchronously Disable Internal Clock Circuitry Asynchronous Master Reset Asynchronously Applied to Swallow a Data Bit SINA SINA SINB SINB SINSEL 1:2 DEMUX CKEN T C R Q 1:2 DEMUX 1:2 DEMUX Q1 Q5 Q3 Q7 PCLK PCLK 1:2 DEMUX 1:2 DEMUX 1:2 DEMUX Q0 Q4 Q2 Q6 High Low Select SINA Input Q: PCLK = 8:1 CLK: Q = 1:2 CLK Q Synchronously Enable Internal Clock Circuitry Synchronous Enable Normal Conversion Process
VEE
T C R
Q SYNC Control Logic DIV2 DIV2
1:2 DEMUX
CLK
CLK CKSEL RESET
Figure 3. Logic Diagram
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MC10EP445, MC100EP445
Table 3. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pull-up Resistor ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 2 N/A Value 75 kW N/A > 2 kV > 200 V > 2 kV Pb-Free Pkg Level 2 Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP-32 QFN-32 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in 993 Devices
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 2S2P <2 to 3 sec @ 248C <2 to 3 sec @ 260C 32 LQFP 32 LQFP 32 LQFP QFN-32 QFN-32 QFN-32 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 31 27 12 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC10EP445, MC100EP445
Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current Input LOW Current 0.5 Min 95 2165 1365 2090 1365 1790 2.0 1890 Typ 119 2290 1490 Max 143 2415 1615 2415 1690 1990 3.3 Min 98 2230 1430 2155 1460 1855 2.0 1955 25C Typ 122 2355 1555 Max 146 2480 1680 2480 1755 2055 3.3 Min 100 2290 1490 2215 1490 1915 2.0 2015 85C Typ 125 2415 1615 Max 150 2540 1740 2540 1815 2115 3.3 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 3. All loading with 50 W to VCC - 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current (Note 6) Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 8) Input HIGH Current Input LOW Current 0.5 Min 95 3865 3065 3790 3065 3490 2.0 3590 Typ 119 3990 3190 Max 143 4115 3315 4115 3390 3690 5.0 Min 98 3930 3130 3855 3130 3555 2.0 3655 25C Typ 122 4055 3255 Max 146 4180 3380 4180 3455 3755 5.0 Min 100 3990 3190 3915 3190 3615 2.0 3715 85C Typ 125 4115 3315 Max 150 4240 3440 4240 3515 3815 5.0 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 6. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 7. All loading with 50 W to VCC - 2.0 V. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP445, MC100EP445
Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 9)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current (Note 10) Output HIGH Voltage (Note 11) Output LOW Voltage (Note 11) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) Input HIGH Current Input LOW Current 0.5 Min 95 -1135 -1935 -1210 -1935 -1510 -1410 Typ 119 -1010 -1810 Max 143 -885 -1685 -885 -1610 -1310 0.0 Min 98 -1070 -1870 -1145 -1870 -1445 -1345 25C Typ 122 -945 -1745 Max 146 -820 -1620 -820 -1545 -1245 0.0 Min 100 -1010 -1810 -1085 -1810 -1385 -1285 85C Typ 125 -885 -1685 Max 150 -760 -1560 -760 -1485 -1185 0.0 Unit mA mV mV mV mV mV V
VEE+2.0
VEE+2.0
VEE+2.0
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Input and output parameters vary 1:1 with VCC. 10. Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 11. All loading with 50 W to VCC - 2.0 V. 12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 13)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 14) Output LOW Voltage (Note 14) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 15) Input HIGH Current Input LOW Current 0.5 Min 95 2155 1355 2075 1355 1775 2.0 1875 Typ 119 2280 1480 Max 143 2405 1605 2420 1675 1975 3.3 Min 98 2155 1355 2075 1355 1775 2.0 1875 25C Typ 122 2280 1480 Max 146 2405 1605 2420 1675 1975 3.3 Min 100 2155 1355 2075 1355 1775 2.0 1875 85C Typ 125 2280 1480 Max 150 2405 1605 2420 1675 1975 3.3 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 14. All loading with 50 W to VCC - 2.0 V. 15. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP445, MC100EP445
Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 16)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current (Note 17) Output HIGH Voltage (Note 18) Output LOW Voltage (Note 18) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 19) Input HIGH Current Input LOW Current 0.5 Min 95 3855 3055 3775 3055 3475 2.0 3575 Typ 119 3980 3180 Max 143 4105 3305 4120 3375 3675 5.0 Min 98 3855 3055 3775 3055 3475 2.0 3575 25C Typ 122 3980 3180 Max 146 4105 3305 4120 3375 3675 5.0 Min 100 3855 3055 3775 3055 3475 2.0 3575 85C Typ 125 3980 3180 Max 150 4105 3305 4120 3375 3675 5.0 Unit mA mV mV mV mV mV V
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 17. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 18. All loading with 50 W to VCC - 2.0 V. 19. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 20)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current (Note 21) Output HIGH Voltage (Note 22) Output LOW Voltage (Note 22) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 23) Input HIGH Current Input LOW Current 0.5 Min 95 -1145 -1945 -1225 -1945 -1525 -1425 Typ 119 -1020 -1820 Max 143 -895 -1695 -880 -1625 -1325 0.0 Min 98 -1145 -1945 -1225 -1945 -1525 -1425 25C Typ 122 -1020 -1820 Max 146 -895 -1695 -880 -1625 -1325 0.0 Min 100 -1145 -1945 -1225 -1945 -1525 -1425 85C Typ 125 -1020 -1820 Max 150 -895 -1695 -880 -1625 -1325 0.0 Unit mA mV mV mV mV mV V
VEE + 2.0
VEE + 2.0
VEE + 2.0
IIH IIL
150 0.5
150 0.5
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Input and output parameters vary 1:1 with VCC. 21. Required 500 lfpm air flow when using -5.0 V power supply. For (VCC - VEE) > 3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC - VEE operation at v 3.3 V. 22. All loading with 50 W to VCC - 2.0 V. 23. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC10EP445, MC100EP445
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 24)
-40C Symbol fmax tPLH, tPHL ts th tRR/tRR2 tPW tJITTER Characteristic Maximum Input CLK Frequency (See Figure 13. Fmax/JITTER) Propagation Delay to Output Differential Setup Time Hold Time CKSEL = LOW CKSEL = HIGH CLK to Q CLK TO PCLK Min 2.0 2.8 1280 1000 -400 100 533 45 350 RESET 400 1.5 1.0 1.5 150 100 100 800 180 180 1200 400 250 150 100 100 800 200 200 Typ 2.5 3.3 1475 1240 -459 50 474 -35 180 1710 1490 Max Min 2.0 2.8 1335 1050 -420 100 550 45 350 400 1.5 1.0 2.0 1200 400 300 150 125 125 800 230 230 25C Typ 2.5 3.3 1557 1310 -479 50 490 -35 180 1795 1580 Max Min 1.7 2.8 1450 1140 -440 100 560 45 350 400 1.5 1.5 2.5 1200 425 325 85C Typ 2.2 3.3 1663 1420 -492 50 508 -35 180 1950 1710 Max Unit GHz ps ps ps ps ps ps
SINA, B+ TO CLK+ (Figure 5) CKEN+ TO CLK- (Figure 6) CLK+ TO SINA, B- (Figure 5) CLK- TO CKEN (Figure 6)
Reset Recovery (Figure 4) Minimum Pulse Width
RMS Random Clock Jitter @ 2.0 GHz CLK_SEL LOW @ 2.5 GHz CLK_SELF HIGH @ 3.0 GHz CLK_SEL HIGH Input Voltage Swing (Differential Configuration) (Note 25) Output Rise/Fall Times (20% - 80%) Q/Q PCLK/PCLK
VPP tr tf
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 24. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 25. VPP(min) is the minimum input swing for which AC parameters are guaranteed.
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MC10EP445, MC100EP445
Reset
tRR
CLK CLK
Figure 4. Reset Recovery
CLK
Data Setup Time
+ ts
-
Data Hold Time
- th
+
Figure 5. Data Setup and Hold Time
CLK
CKEN Setup Time
+ ts
-
CKEN Hold Time - th
+
Figure 6. CKEN Setup and Hold Time
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MC10EP445, MC100EP445
APPLICATION INFORMATION The MC10/100EP445 is an integrated 1:8 serial to parallel converter with two modes of operation selected by CKSEL (Pin 7). CKSEL HIGH mode only latches data on the rising edge of the input CLK and CKSEL LOW mode latches data on both the rising and falling edge of the input CLK. CKSEL LOW is the open default state. Either of the two differential input serial data path provided for this device, SINA and SINB, can be chosen with the SINSEL pin (pin 25). SINA is the default input path when SINSEL pin is left floating. Because of internal pull-downs on the input pins, all input pins will default to logic low when left open.
RESET (Asynchronous Reset)
The two selectable serial data paths can be used for loop-back testing as well as the bit error testing. Upon power-up, the internal flip-flops will attain a random state. To synchronize multiple flip-flops in the device, the Reset (pin 1) must be asserted. The reset pin will disable the internal clock signal irrespective of the CKEN state (CKEN disables the internal clock circuitry). The device will grab the first stream of data after the falling edge of RESETA, followed by the falling edge of CLKA, on second rising edge of CLKA in either CKSEL modes. (See Figure 6)
RESET (Synchronous ENABLE)
CLK RESET PCLK
A A
A
Figure 7. Reset Timing Diagram
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MC10EP445, MC100EP445
For CKSEL LOW operation, the data is latched on both the rising edge and the falling edge of the clock and the time from when the serial data is latchedA to when the data is seen on the parallel outputA is 6 clock cycles (see Figure 8).
Number of Clock Cycles from Data Latch to Q 1 2 3 4 5 6 CLK SINA RESET CKEN CKSEL PCLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
A
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9 D10 D11 D12 D13 D14 D15
D16 D17 D18 D19 D20 D21 D22 D23
Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL LOW
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MC10EP445, MC100EP445
Similarly, for CKSEL HIGH operation, the data is latched only on the rising edge of the clock and the time from when the serial data is latchedA to when the data is seen on the parallel outputA is 12 clock cycles (see Figure 9).
1 Number of Clock Cycles from Data Latch to Q 2 3 4 5 6 7 8 9 10 11 12
A
CLK SINA RESET CKEN CKSEL PCLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
A
D0 D1 D2 D3 D4 D5 D6 D7
Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL HIGH
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MC10EP445, MC100EP445
To allow the user to synchronize the output byte data correctly, the start bit for conversion can be moved using the SYNC input pin (pin 2). Asynchronously asserting the SYNC pin will force the internal clock to swallow a clock pulse, effectively shifting a bit from the Qn to the Qn-1 output as shown in Figure 10 and Figure 11. For CKSEL LOW, a single pulse applied asynchronously for two consecutive
2 Clock Cycles for SYNC 1 2
clock cycles shifts the start bit for conversion from Qn to Qn-1. The bit is swallowed following the two clock cycle pulse width of SYNCA on the next triggering edge of clockA (either on the rising or the falling edge of the clock). Each additional shift requires an additional pulse to be applied to the SYNC pin. (See Figure 10)
Next Triggering Edge of Clock Bit D8 is Swallowed
A
CLK SINA CKSEL PCLK SYNC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
A
D0 D1 D2 D3 D4 D5 D6 D7 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
Figure 10. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL LOW
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MC10EP445, MC100EP445
For CKSEL HIGH, a single pulse applied asynchronously for three consecutive clock cycles shifts the start bit for conversion from Qn to Qn-1. The bit is swallowed following the three clock cycle pulse width of SYNCA on the next
3 Clock Cycles for Sync 123 CLK SINA SYNC PCLK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
D0 D1 D2 D3 D4 D5 D6 D7
triggering edge of clockA (on the rising edge of the clock only). Each additional shift requires an additional pulse to be applied to the SYNC pin. (See Figure 11)
Next Triggering Edge of Clock Bit D8 is Swallowed
A
D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
A
Figure 11. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL HIGH
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MC10EP445, MC100EP445
The synchronous CKEN (pin 3) applied with at least one clock cycle pulse length will disable the internal clock signal. The synchronous CKEN will suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the falling
Internal Clock Disabled
edge of CLK will suspend all activities. The first data bit will clock on the rising edge, since the falling edge of CKEN followed by the falling edge of the incoming clock triggers the enabling of the internal process. (See Figure 12)
Internal Clock Enabled
CLK CKEN PCLK CKSEL
Figure 12. Timing Diagram with CKEN with CKSEL HIGH
The differential PCLK output (pins 22 and 23) is a word framer and can help the user to synchronize the parallel data outputs. During CKSEL LOW operation, the PCLK will provide a divide by 4-clock frequency, which frames the serial data in period of PCLK output. Likewise during CKSEL HIGH operation, the PCLK will provide a divide by 8-clock frequency. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input
conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor, which will limit the current sourcing or sinking to 0.5mA. When not used, VBB should be left open. Also, both outputs of the differential pair must be terminated (50 W to VTT = VCC - 2 V) even if only one output is used.
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MC10EP445, MC100EP445
1000 900 VOUTpp (mV) 800 700 600 500 400 300 200 100 0 (JITTER) CKSEL LOW CKSEL HIGH 10 9 8 7 6 5 4 3 2 1 JITTEROUT ps (RMS)
0
500
1000
1500
2000
2500
3000
3500
INPUT CLK FREQUENCY (MHz)
Figure 13. Fmax/Jitter
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 3.0 V
Figure 14. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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EE EE
EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE
MC10EP445, MC100EP445
ORDERING INFORMATION
Device MC10EP445FA MC10EP445FAG MC10EP445FAR2 MC10EP445FAR2G MC10EP445MNG MC10EP445MNR4G MC100EP445FA MC100EP445FAG MC100EP445FAR2 MC100EP445FAR2G MC100EP445MNG MC100EP445MNR4G Package LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) LQFP-32 LQFP-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) Shipping 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 74 Units / Rail 1000 / Tape & Reel 250 Units / Tray 250 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel 74 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10EP445, MC100EP445
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE B
A
25 4X
A1
32
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V V1
AE P AE
17
DETAIL Y
BASE METAL
N
9
S
8X
M_
R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 _ REF 12 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 _ REF 12 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
K
Q_
GAUGE PLANE
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
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0.20 (0.008)
9
-Z- S1
0.20 (0.008) AC T-U Z
F
D
M
4X
AC T-U Z
DETAIL Y
-T-, -U-, -Z-
EE EE EE
MC10EP445, MC100EP445
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
8
1 32 X b 0.10 C A B 32 25
0.05 C BOTTOM VIEW
32 X
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
TOP VIEW SIDE VIEW
9
PIN ONE LOCATION
E
(A3) A A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
D2
K
17 32 X
SOLDERING FOOTPRINT*
5.30 3.20
E2
24 32 X
0.63 e 3.20 5.30
0.28
0.50 PITCH
28 X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC10EP445/D

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